Every few years, a chip AMD quietly buried climbs back out of the ground. This week it’s the Ryzen 9 5900X3D, a 12-core Zen 3 processor that never reached a store shelf, showing up in a Chinese forum post with a cache configuration nobody had seen before. If you’ve spent any time around AM4 enthusiasts, you already know why that got people talking. For a few years the community’s favorite what-if was a 5900X with 3D V-Cache bolted on. Now there’s at least one real chip that looks a lot like that fantasy.
A quick note on sourcing before we get into it. Everything about this sample traces back to a single forum thread on Chiphell, relayed by IT Home and then picked up by Guru3D, TechPowerUp, VideoCardz, and others. AMD hasn’t confirmed anything. Treat the specifics below as reported, not verified.
What actually surfaced
According to the Chiphell post, the processor carries the OPN code 100-000000652 and identifies as an AM4 part from AMD’s Vermeer family, built on Zen 3. The reported specs are 12 cores and 24 threads, a 105W TDP, and a listed maximum frequency of up to 4.85GHz. The headline number is the cache: 128MB of L3 in total, split as 96MB on one chiplet and 32MB on the other.
That split is the interesting part. A normal Ryzen 9 5900X has two core chiplets (CCDs), each with 32MB of L3. Stack a 64MB 3D V-Cache die on one of them and that chiplet jumps to 96MB while the other stays at 32MB. Add it up and you get 128MB. So this is a one-stack design: only half the cores get the big cache.
The owner’s CPU-Z screenshots reportedly show the chip running around 4.7GHz, and other write-ups cite readings in the 4.65 to 4.73GHz range in monitoring tools. Worth remembering that engineering samples can report odd numbers, so I’d treat the 4.85GHz figure as a label rather than a measured result.
It’s picky about firmware, which tells you something
The forum user reportedly couldn’t get the sample to boot on the latest motherboard BIOS, where it threw a Q-Code 90, and only got it running on an older UEFI release carrying SMU firmware version 56.70.0. Nobody has promised support, and that’s normal for engineering samples, which are built against firmware that was never meant to ship to retail users. Guru3D suggests the limitation could reflect the sample’s early development status or missing firmware support for this particular configuration. That reading makes sense to me. A cache layout that never became a product is exactly the kind of thing that stops getting BIOS attention once the program is shelved.
How this differs from the prototypes AMD already showed us
This isn’t the first unreleased 5900X3D we’ve heard about. In 2023, Gamers Nexus toured AMD’s Austin lab and was shown working 12-core and 16-core Zen 3 prototypes, effectively a 5900X3D and a 5950X3D, with 3D V-Cache on both chiplets. That gave them 192MB of L3 each. Those chips ran lower clocks than their regular siblings: the 5900X3D prototype reportedly topped out at a 4.4GHz boost, and the 5950X3D at 4.1GHz, with voltage and thermal limits cited as the reason.
Here’s how the three designs compare:
| Chip | L3 layout | Total L3 | Reported boost | Status |
|---|---|---|---|---|
| Ryzen 9 5900X3D (new ES) | 96MB + 32MB | 128MB | ~4.7GHz observed, 4.85GHz listed | Unreleased |
| Ryzen 9 5900X3D (2023 lab prototype) | 96MB + 96MB | 192MB | Up to 4.4GHz | Unreleased |
| Ryzen 7 5800X3D (retail) | 96MB, single CCD | 96MB | Up to 4.5GHz | Released April 2022, $449 |
The new sample’s higher frequency is the detail I keep coming back to. If the numbers hold up, stacking cache on only one chiplet may have let AMD run it faster than the dual-stack version, which fits what you’d expect from a design with half as much hot silicon under the cache. One outlet speculated that this sample could even post-date the dual-stack prototypes, meaning AMD may have iterated toward it. That’s speculation, and I’d file it there, but it’s a coherent story: try the maximalist version, find the clocks suffer, back off to a one-stack design.
Why AMD never shipped any of them
AMD’s only retail Zen 3 X3D chip for years was the eight-core Ryzen 7 5800X3D, which launched April 20, 2022 at $449 with a 3.4GHz base, 4.5GHz boost, 96MB of L3, and a 105W TDP. AMD pitched it as roughly 15 percent faster than the Ryzen 9 5900X in games on average. Notice the awkward subtext there: the 8-core part beat the 12-core flagship at gaming. That’s the whole reason a 12-core X3D was hard to justify.
Several threads of reasoning have been reported over the years:
- Games don’t use two chiplets well. Most games lean on eight or fewer cores, and schedulers try to keep game threads on one CCD. Crossing to the other chiplet’s cache costs real latency, so extra cache on the second CCD does little for gaming, a point AMD made to HardwareLuxx when asked about its later Ryzen 9000 chips.
- Clocks took a hit. The dual-stack prototypes ran below their non-X3D counterparts, according to coverage of the Gamers Nexus tour.
- Cost. AMD told HardwareLuxx that a dual-cache chip was simply not economically viable and wouldn’t benefit gamers enough to justify the price. That statement was about Ryzen 9000, but the same math applied on AM4 with a first-generation stacking process.
My own read, and this one is analysis rather than reporting: a one-stack 5900X3D would have had its own problem. You’d have a chip where one chiplet has triple the cache and the other doesn’t, and games would need to land on the right cores. AMD later built software to steer games toward the cache chiplet on AM5, but that machinery didn’t exist in the AM4 era. Shipping a hybrid layout without it could have produced inconsistent results for buyers, and the 5800X3D already gave AMD a clean halo product with no such wrinkles.
The punchline: AMD eventually built this chip anyway, on a newer platform
Here’s what makes the timing of this leak funny. The layout in this engineering sample, one chiplet with stacked cache and one without, is exactly what AMD ended up shipping on AM5. The Ryzen 9 7950X3D, 7900X3D, 9950X3D, and 9900X3D all use a single stacked chiplet. The 9950X3D, for example, carries about 128MB of L3 spread across its two CCDs. That’s the same total as this Zen 3 sample.
And the dual-stack idea AMD shelved on Zen 3? It came back this year. On April 22, 2026, AMD launched the Ryzen 9 9950X3D2 Dual Edition, the first desktop processor with 3D V-Cache on both chiplets: 16 cores, 208MB of total cache, a 200W TDP, a boost clock up to 5.6GHz, and an $899 price. AMD’s second-generation 3D V-Cache, which places the cache die beneath the compute chiplet instead of on top, is what made this practical, since it eased the thermal penalty that held back first-generation stacking. So the story runs full circle: the maximalist design AMD tried on Zen 3 and abandoned finally shipped four years after the 5800X3D, only once the packaging had caught up with the idea.
Does this matter if you can’t buy it?
Not for your next build, no. This is an archival curiosity, and there’s no sign AMD plans to release anything like it. If one of these ever resurfaces in a collector’s hands, the realistic outcome is a screenshot, not a benchmark suite, especially given how fussy the firmware requirements apparently are. I’d also be wary of anyone trying to sell you a “5900X3D.” Engineering samples circulate in secondhand markets, but they come with real compatibility risk and no warranty, and a counterfeit or relabeled 5900X is a plausible scam at this point.
What it does give us is a small window into how AMD worked through its 3D V-Cache decisions. The company evidently built at least two different 12-core X3D designs on Zen 3, tested them, and chose not to commercialize either. That’s a satisfying piece of confirmation for anyone who suspected the 5800X3D’s solo act wasn’t for lack of trying.
What we still don’t know
A lot, really. No one has published benchmarks. We don’t know how many of these samples exist, whether the 4.85GHz figure is real, or how the one-stack layout actually performed in games compared to the 5800X3D. We also don’t know whether more of these configurations are sitting in AMD’s labs, though the pattern suggests there probably are. If a benchmark run does surface, it’ll be the first real data point on whether the one-stack Zen 3 design would have been worth shipping.
